2
RF Device Data
Freescale Semiconductor
MRF5P21045NR1
Table 3. ESD Protection Characteristics
Test Methodology
Class
Human Body Model (per JESD22-A114)
1C (Minimum)
Machine Model (per EIA/JESD22-A115)
A (Minimum)
Charge Device Model (per JESD22-C101)
IV (Minimum)
Table 4. Moisture Sensitivity Level
Test Methodology
Rating
Package Peak Temperature
Unit
Per JESD 22-A113, IPC/JEDEC J-STD-020
3
260
°C
Table 5. Electrical Characteristics (TC
= 25
°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
Off Characteristics (1)
Zero Gate Voltage Drain Leakage Current
(VDS
= 65
Vdc, VGS
= 0 Vdc)
IDSS
?
?
10
μAdc
Zero Gate Voltage Drain Leakage Current
(VDS
= 28 Vdc, V
GS
= 0 Vdc)
IDSS
?
?
1
μAdc
Gate-Source Leakage Current
(VGS
= 5 Vdc, V
DS
= 0 Vdc)
IGSS
?
?
1
μAdc
On Characteristics (1)
Gate Threshold Voltage
(VDS
= 10 Vdc, I
D
= 120
μAdc)
VGS(th)
2
?
3.5
Vdc
Gate Quiescent Voltage
(VDS
= 28 Vdc, I
D
= 500
mAdc)
VGS(Q)
?
3.8
?
Vdc
Fixture Gate Quiescent Voltage (2)
(VDD
= 28 Vdc, I
D
= 500 mAdc, Measured in Functional Test)
VGG(Q)
6
7.6
10
Vdc
Drain-Source On-Voltage
(VGS
= 10 Vdc, I
D
= 1.2
Adc)
VDS(on)
0.2
0.3
0.35
Vdc
Dynamic Characteristics (1,3)
Reverse Transfer Capacitance
(VDS
= 28 Vdc
±
30 mV(rms)ac @ 1 MHz, V
GS
= 0 Vdc)
Crss
?
0.9
?
pF
Output Capacitance
(VDS
= 28 Vdc
±
30 mV(rms)ac @ 1 MHz, V
GS
= 0 Vdc)
Coss
?
124
?
pF
Input Capacitance
(VDS
= 28 Vdc
±
30 mV(rms)ac @ 1 MHz, V
GS
= 0 Vdc)
Ciss
?
247
?
pF
Functional Tests (1)
(In Freescale Test Fixture, 50 ohm system) V
DD
= 28
Vdc, IDQ
= 500
mA, Pout
= 10
W Avg., f1 = 2112.5 MHz,
f2 = 2122.5 MHz and f1 = 2157.5 MHz, f2 = 2167.5 MHz, 2-Carrier W-CDMA, 3.84 MHz Channel Bandwidth Carriers. ACPR measured
in 3.84 MHz Channel Bandwidth @ ±5 MHz Offset. IM3 measured in 3.84 MHz Bandwidth @ ±10 MHz Offset. PAR = 8.5 dB @ 0.01%
Probability on CCDF.
Power Gain
Gps
13.5
14.5
16.5
dB
Drain Efficiency
ηD
23.5
25.5
?
%
Intermodulation Distortion
IM3
?
-37
-35
dBc
Adjacent Channel Power Ratio
ACPR
?
-39
-37
dBc
Input Return Loss
IRL
?
-12
-8
dB
1. Measurement made with device in single-ended configuration. (See Figure 4, Possible Circuit Topologies)
2. VGG
= 2 x V
GS(Q). Parameter measured on Freescale Test Fixture, due to resistive divider network on the board. Refer to Test Circuit
schematic.
3. Part internally matched both on input and output.
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